The present invention relates to the manufacture of semiconductor devices, and in particular, to the manufacture of conductor layers utilized in advanced semiconductor products, such as memories.
Semiconductor memory devices are comprised of an array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. A charged capacitor corresponds to a logical state of xe2x80x9c1xe2x80x9d and an uncharged capacitor corresponds to a logical state of xe2x80x9c0.xe2x80x9d Word lines activate access transistors, so that the logical state of a memory cell can be read. Gates of multiple transistors are formed as one word line.
An example of a word line""s application is in a dynamic random access memory (DRAM). In a DRAM, a common word line, used to access memory cells, is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide (SiO2), known as gate oxide. Then, a word line is formed on the gate oxide layer as a two-layer stack, comprising silicon (or polysilicon), coated with a conductor material. The most common two-layer stack used in the industry is a layer of polysilicon, coated with a tungsten silicide layer. Tungsten silicide is used because of its good integration properties, such as providing good thermal stability, stability during source/drain oxidation, and stability during dry etching, as well as having a low resistivity. Although titanium silicide is approximately 75% less resisitive than tungsten silicide, it has not been used extensively in two-layer stacks because it is not as thermally stable. Titanium silicide tends to agglomerate during subsequent high temperature processing steps. Alternatively, a metal is used instead of a silicide for the conductor layer.
Forming high conductivity films on word lines is one attempt to decrease the resistivity of a word line. Such films are commonly formed of a refractory metal silicide, such as titanium silicide (TiSi2). Titanium is preferably used as the refractory metal component because it has the ability to reduce oxygen, which remains on surfaces in the form of native oxides. Native oxides are reduced to titanium oxide by titanium. Native oxides degrade interface stability, and often cause device failure if not removed.
However, several problems occur with the use of TiSi2 in ULSI applications. At higher temperatures subsequent processing temperatures, TiSi2 has a tendency to agglomerate into two different phases, C54 and C49, which have different lattice structures. The C54 phase agglomerates at the interfaces between C49-TiSi2 and silicon (or polysilicon). While this is undesirable due to the increased resistance associated with agglomeration, the TiSi2 phase formed at higher temperatures, C54, is more stable and has a much lower resistivity than the C49 metastable phase formed at lower temperatures.
Another problem with using TiSi2 at higher temperatures is that the high-temperature phase, C54, has a grain size typically ranging from 0.3 to over 1.0 microns, which prohibits it from being used in sub-0.25 micron word line applications. However, it is always desirable to form a phase having the lowest free energy at a particular grain size, so that it is the most stable. FIG. 1 illustrates how free energy, xcex94Gf(xcex3), is a function of grain size, r. Free energy, xcex94Gf(xcex3), as a function of grain size, r, is divided into three regions: A, B, and C. The most stable phase at a given grain size is that which has the lowest free energy. Both regions A and B are in the sub-micron range. In the sub-micron range, the free energy of C54 is greater than that of C49, due to the larger surface energy of C54.
In ultra large scale integrated (ULSI) circuits, a highly conductive word line is necessary to improve circuit density and performance. To date, word line resistance is one of the primary limitations of achieving faster ULSI circuits. A method for decreasing the resistivity of word lines is needed for use in ULSI applications. In order to use the C54-TiSi2 phase in ULSI circuits, particularly in 256 Megabit DRAMs and other devices requiring sub-0.25 micron line widths, it is necessary that the grain size be reduced, so that it will be more stable. Due to the increased sensitivity of ULSI circuits, it is important to maintain low resistivity in ULSI devices. There is a need for a stable, low resistivity TiSi2 phase which can be used in sub-0.25 micron word line applications.
A method for forming a word line, which is used in ultra-large scale integrated (ULSI) circuits, produces a lower resistivity word line than those formed using prior art techniques. Resistivity is lowered and grain size of the conductor layer is modified using barrier elements to form a low dose matrix in silicon, or polysilicon. Subsequently annealing the word line stack forms a preferential C54-titanium silicide (TiSi2). C54-TiSi2 is more stable at high temperatures than C49-TiSi2. Use of C54-TiSi2 minimizes problems with C49-TiSi2 agglomerating at higher temperatures. Furthermore, C54-TiSi2 has a much lower resistivity than C49-TiSi2. Sub-0.25 micron word lines are able to be silicided with C54-TiSi2 using the invention, due to modification of TiSi2 grain sizes using the implanted matrix. Previously, the relatively large size of C54-TiSi2 grains, greater than 0.3 microns, prohibited its use in sub-0.25 micron word line applications.